In a conventional communication apparatus, a receiver uses a demultiplexer apparatus, and the demultiplexer apparatus uses a demultiplexer circuit DEMUX. FIG. 1 shows the circuit structure example of a conventional demultiplexer apparatus of a shift register type. Referring to FIG. 1, the conventional demultiplexer apparatus of the shift register type has D-type flip-flops 501 to 508 connected as a cascade of a plurality of stages (8 stages in the example shown in FIG. 1). A latching circuit 51 receives in parallel the outputs of the D-type flip-flops 501 to 508. Data is shifted for each clock through the D-type flip-flops. Thus, the number of process bits per clock is one. Such a technique is disclosed in, for example, IEICE Trans. Electron, (Vol. E78-C, No.12, 1995, p.1746): conventional reference 1).
FIGS. 2A and 2B show the circuit structure example of a conventional demultiplexer apparatus of a tree type. Referring to FIG. 2A, in the conventional demultiplexer apparatus of the tree type, 1:2 demultiplexers DEMUX 60 (601 to 607) are hierarchically arranged. As shown in FIG. 2B, the 1:2 demultiplexer DEMUX 601 at a first stage defines an operational rate and alternately reads the data for the flip-flops in two systems. Thus, it can process the data of two bits for each clock. Such a technique is disclosed in, for example, IEICE Trans. Electron, (Vol. E78-C, No.12, 1995, p1746: conventional reference 2).
Also, an over-sampling method is proposed in which one data is read a plurality of times. Such a technique is disclosed in, for example, Symp. On VLSI Circuits Digest of Technical papers (1997, p.71: conventional reference 3).
In a method of using binary logic flip-flops in an input unit, in any case of the logics, the input section is operated as schematically shown in FIGS. 3A and 3B. In FIG. 3A, a switch SW1 is closed (turned on) in a former part of a one-clock period, and a switch SW2 is opened (turned off). An input data is sampled by a capacitor C. As shown in FIG. 3B, the switch SW1 is opened (turned off) in a latter part of the one-clock period, and the switch SW2 is closed (turned on). The data held by the capacitor C is sent to a flip-flop at a next stage (not shown).
If the frequency of the clock used for the sampling is the maximum operational frequency of a transistor to be used, in order to carry out the accurate sampling, one sampling requires at least a sampling time equal to half the clock period. In short, the data rate that can be attained by this method is (the maximum operational frequency×2).
In the over-sampling method, as shown in FIGS. 4A to 4E, the data (DATA) is sampled the plurality of times at timings slightly different from each other. That is, multi-phase clocks CLK0 to CLK3 are used to carry out the sampling. The data is recovered from the plurality of sample data by using a weighting function. In the example shown in FIGS. 4A to 4E, the data is sampled at edges of a 4-phase clock, and 1 is recovered as a recovery data (Decision Data) from 0111. Consequently, in this case, the possible data rate is greater than (the maximum operational frequency×2).
By the way, in FIGS. 4A to 4E, the waveform of the clocks CLK0 to CLK3 is illustrated as a rectangular wave. However, if a transistor is used such that the frequency of the clock is close to its maximum operational frequency, the waveform of the clock becomes a sine wave. For this reason, the sample data contains an error because of the influence of the data before and after the data of a target to be read. This results in a problem that it is difficult to reduce an error rate.
In conjunction with the above-mentioned description, a sign converting circuit is disclosed in Japanese Laid Open Patent Application (JP-A P2000-165246). In the sign converting circuit for optical dual binary transmission in this reference, a bit distributor receives a high speed input signal and distributes this signal into low speed signals into N (N is an integer of 2 or more) systems. N sign converters are provided for the distributed low signals of the N systems, and each perform the sign conversion on the low speed signals, respectively. A bit synthesizer receives the low speed signals after the conversions of the N signs respectively outputted from the N sign converters, and logically operates and synthesizes those respective low speed signals, and then generates a high speed output signals after the sign conversions. Each of the sign converting circuits includes an EXOR circuit for generating an EXOR output of the corresponding low speed signal and a delayed feedback signal one bit before.